In 2025, Trump's return to the White House will usher in the 3.0 phase of the US-China trade and technology war, influencing Taiwan's fate and the global landscape. Semiconductors are key to this. To understand how both sides will react, we need a deeper and more concrete understanding of semiconductors. Back in 2022, former US President Biden imposed chip sanctions on China, not only pressuring ASML to restrict China's access to exposure machines but also banning the export of EDA tools for sub-3nm GAAFETs to China. But without EDA, will China truly be unable to design high-end chips? A new year calls for a new beginning. Facing mountains of work, this year you don't have to struggle alone. The Pan-Science Academy provides all office workers with a "5-minute AI Lazy Package"—a lifesaver for civil servants. Whether it's automating document processing, designing creative promotional graphics, or data analysis, AI can easily handle it all by yourself. The course is taught by our partner, senior AI instructor AJ, who has over a hundred training sessions for government agencies. AI technologies you can and can't imagine will appear in the course to help you solve your pain points. Imagine a less stressful work environment with dramatically increased efficiency, giving you more time to spend with your family and enjoy life. We've also prepared a special New Year's gift: all views on this video will be instantly deducted from your bill by entering this amount at checkout, making your learning even more worthwhile. New Year, new beginnings! Enroll in our course and start a new year of high-efficiency living. EDA, commonly known as Electronic Design Automation, is a set of tools for manufacturing integrated circuit hardware. It is a set of computer-aided design flow that must be used in the manufacture of integrated circuit hardware, which integrates many software and databases. Why is it necessary? Why is it necessary? As we all know, all electronic products, including cell phones, cars, home appliances, and weapons, are filled with various integrated circuits (ICs). For a 3nm process, approximately 250 million transistors can be loaded per square millimeter. The diameter of the SARS-CoV-2 virus is 80-120 nanometers; in other words, each transistor is about one size smaller than a virus. With so many transistors crammed into the integrated circuit, it's unlikely that the chip designer could arrange them one by one. One by one, so in order to make the design smooth and efficient, it is necessary to participate through the EDA tool. Just like assembling a LEGO City model, the EDA can provide the pre-built traffic light components. The designer does not have to manually assemble one red lego and one green lego. There will even be a completed, fully designed Opera House that you can directly choose. In the chip-designing situation, it is to let the EDA itself find the circuit from the database to meet the functional requirements and install it for you. Planning the integrated circuit is important, but more importantly, EDA can provide simulation verification. Through continuous simulation and debugging, we can know if the entire IC layout is truly working. For the designer's goal, EDA can optimize the IC layout by simulating it for different goals, such as the highest performance, the smallest area, or the lowest heat generation of the chip. In other words, you can think of IC design companies like MediaTek as architects. EDA is like an illustrator for graphic designers; they use EDA to draw the entire blueprint, allowing you to draw a Bezier curve. But whether the house can be built or not remains to be seen. Whether or not construction can be completed depends on discussions with TSMC and Samsung, who are responsible for the construction. Most of the high-end components will be provided by EDA design, or developed and designed by silicon IP companies that specialize in designing high-end components, and then authorized to IC companies such as TSMC and Samsung. When you place an order with TSMC and Samsung, you can be more confident in using their designed components. Having understood what EDA is, let's take a look at what the EDA market looks like. Let's also look at China, which is affected by the ban, and how the semiconductor industry has developed in China. In terms of market share, 70-80% of the world's largest EDA tool manufacturers use EDA tools from the United States, namely Synopsys, Cadence, and Siemens EDA. These large companies have over 30 years of experience, high customer loyalty, and readily available high-end component IP. Their EDA development is involved in the design and manufacturing of many high-performance chips. In contrast, the largest Chinese brand... EDA companies like Cellix and Empyream have less than 20 years of experience and are still stuck in mature processes of 28nm or larger. This makes them significantly less competitive. Each generation of nanometer transistor fabrication requires a dedicated EDA because the components used are different, and therefore the EDA algorithm will also differ. In other words, there is no way to mix a 5nm EDA with a 3nm design or process. To develop a new EDA, you need a corresponding wafer fab. To cooperate and verify the accuracy of computer simulations through the manufacturing process. Currently, TSMC and Samsung dominate the advanced process. They also assist IC design companies in optimizing design content to continuously improve chip performance, stability, or reduce manufacturing costs. China does not have a mastery of advanced process technology foundries, so developing EDA below 28nm faces a very high threshold. In addition, after the U.S. ban and South Korea's joining "Chip 4". Samsung's fabs in China are restricted from expanding their advanced process lines. This has also halted China's advanced process R&D. To understand GAAFET, we need to start with the smallest unit on the chip: a single transistor. Integrated circuits (ICs) use semiconductors with both conductive and insulating properties to control the switch through an electric field. Currently, the most widely used field-effect transistor (FET ) for high-end ICs is the FinFET, while GAAFET is the next-generation design. To understand the different transistor designs used in next-generation design, one should first look at the original prototype, the Planar FET. Each transistor acts as a switch in the circuit, controlling the flow of electrons from the source. These electrons are blocked by the gate, which acts like a current baffle. Electrons only pass through the source to the drain when voltage is applied to the gate. This passage is determined by the conditions that prevent electrons from passing through. This constructs the digital 1 and 0. The different processes we often hear about, such as 40nm and 28nm, actually refer to the gate length. This brings us to one of Intel's founders, Gordon Moore. He proposed the Law of Semiconductor Growth: the number of transistors that can be accommodated on an integrated circuit roughly doubles every 18 months. Therefore, to accommodate more transistors in the same area, the key is to make the transistors smaller. A 50% reduction in area translates to a reduction in edge length of about 70%. In 2001, the manufacturing process was 130nm, followed by 90nm in 2003. In 2003 came the 90nm process, followed by 65nm in 2005, 45nm in 2007, and more recently 7nm, 5nm, and 3nm. This allows for the packing of more transistors into the same area, enabling the creation of smaller, more efficient wafers. This is the most critical part of wafer manufacturing. However, as transistors become smaller, the next problem arises: the channels for electron flow narrow, and the oxide layer below the gate becomes thinner. Electrons are prone to leakage because they cannot be shut off properly, leading to tunneling and leakage. This instability causes the chip to overheat and eventually age and become unusable. To improve current control, the contact area between the gate and the channel needs to be increased. Therefore, the 2D Planar FET needs to be replaced with a 3D FinFET to solve the leakage problem. To address the issues of leakage and dynamic power loss, TSMC used FinFETs in its processes from 20nm to 3nm. However, to move down to smaller transistors, FinFETs still faced the problem of insufficient contact area. A new solution emerged – GAAFET ( Gate-all-around) transistor technology. Unlike FinFETs, which have a U-shaped contact area, GAAFET uses a multi-column winding. GAAFETs have a circular shape, but in terms of circumference, increasing the gate contact area is not much larger than the original "U-shaped" area. It can be said that the limit of FinFET is 3nm. Below 3nm, the FinFET process is prone to leakage, making the current unstable and accelerating chip aging due to the heat generated. If you want to develop 3nm ICs, you must use EDA (Electronic Design Automation) for components below 3nm, specifically GAAFETs. The recent U.S. ban directly targets EDA for GAAFETs below 3nm. Sub-3nm GAAFETs mean that China is unable to advance the development and manufacturing of advanced chips. As the manufacturing process continues to shrink, the channels also shorten, resulting in a short-channel effect of leakage, which has plagued the industry since the 20nm era. This is why transistors must change from a planar to a 3D structure. However, in addition to pursuing even smaller 3nm, 2nm, and even 1nm processes, the ultimate goal is to obtain higher performance, more power-saving, thinner, and shorter chips. And it shouldn't be too expensive. In 2020, TSMC and Samsung successively introduced EUV exposure machines from ASML in the Netherlands, which are essential for advanced manufacturing processes. Intel, which was originally lagging behind in the introduction of EUV, also announced that it plans to be the first to use the second-generation EUV exposure machine by 2025. In addition, due to pressure from the United States, China's SMIC was unable to purchase the EUV exposure machine ordered as early as 2018. So why are all the major chip manufacturing companies rushing to purchase EUV? Will the absence of this machine really have a significant impact on advanced chip manufacturing processes ? Today, let's talk about extreme ultraviolet (EUV) lithography machines. Before understanding why TSMC was the first to introduce EUV lithography machines, let's discuss the five steps of the lithography process. First, photoresist is coated onto the silicon wafer. This photosensitive material, similar to that in film cameras, allows light hitting it to be seen. It 's worth mentioning that the current supply of photoresist is mainly from Japan and the United States, accounting for 90% of the market. In 2021, due to the devastating Tohoku earthquake in Japan, some chip manufacturers faced supply disruptions. Therefore, even though TSMC and Samsung have mastered globally leading chip manufacturing technologies, they still rely on photoresist supplies from Japan and the United States. Returning to the lithography process of chips... After applying the photoresist, exposure can begin. The photomask is then attached. On the photomask is the integrated circuit design (one layer) previously created using EDA. When ultraviolet light passes through the photomask, creating light and shadow, it strikes the wafer, forming the circuit diagram image. It's worth noting that one reason TSMC is able to lead in process technology is its photomask cleaning technology, far ahead of other wafer foundries. This technology is advantageous because in the nanoscale chip manufacturing process, even a particle smaller than PM2.5 falling onto the wafer is like a meteorite impact to a nanoscale chip. Next comes the development process. After exposure, based on the different properties of the positive and negative photoresists, unwanted parts of the circuit diagram are removed. If you've ever worked with film cameras, you 'll understand what exposure means. The terms "photolithography" sound familiar, don't they? Actually, lithography, like film cameras, uses the principle of optical imaging. It utilizes the property that light travels in a straight line in a uniform medium. By adjusting the distance between the lens and the film, large images like Taipei 101, the lion, and the elephant are miniaturized onto the film. The ratio of photomask to chip miniaturization is 4:1. The next step in lithography is etching, which etches away the areas without photoresist after exposure. Areas where photoresist was present resist etching, thus forming the circuit structure. After these steps, congratulations! You've etched a patterned wafer. Keep going! Repeat this process more than 50 times. That's right, for a precise, high-end chip to operate smoothly... This process requires several layers of overlay, so the chip is repeated nearly 50 times before it is truly complete. Within the entire lithography process, the most technically demanding, precise, and technologically advanced step is exposure. As we all know, chips are constantly striving for higher performance. From 5 micrometers in the 1980s to 5 nanometers today, the area has shrunk by a million times in just 30 years. This achievement is made possible by the continuous upgrading of lithography technology. As circuit diagrams become increasingly complex and need to be etched onto the wafer, the circuit lines also need to be finer. We also discussed transistor gate length in the EDA bill video. This is one of the factors affecting component size. For those interested in learning more, you can watch our previous video. To shorten the gate length of a transistor, you essentially need to adjust the linewidth and pitch of the light hitting the wafer. This is illustrated in the image. Typically, the pitch between metal layer lines is used as a reference. The smaller the pitch, the smaller the linewidth, and the higher the degree of component miniaturization. How do we pursue the minimum linewidth? Let's start with the core optical resolution formula, where k1 is the process coefficient, λ is the wavelength of the light source used in lithography, from the initial 436 nanometers to DUV 193 nanometers, and the latest EUV has dropped to 13.5 nanometers. sinθ is the angle at which light is focused onto the imaging plane, which is related to the lens assembly specifications, i.e., the lens's numerical aperture (NA). Using a camera analogy, it's similar to how a larger aperture lens improves resolution. We want the half-pixel distance to be as small as possible. The most important aspects of iterative improvements to exposure machines are these two key factors: the wavelength of the light source and the digital aperture (NA) of the lens. Reducing the wavelength of the light source or increasing the NA of the lens can effectively improve optical resolution. Lithography has always focused on improving exposure resolution, aiming to make the linewidth on the wafer smaller—the finer the lines, the better— and the distance between lines smaller, the better. One way to improve this is to increase the lens's focusing angle. The lenses used in exposure machines are much more complex and larger than those in cameras or telescopes we usually use. From the 1990s to 2005, through precise calculations, lenses of various sizes... Various lenses of different thicknesses are precisely stacked together. For example, this 20-nanometer process node DUV exposure machine is a lens module composed of many lenses. It can only be moved by a crane. To continue miniaturization? According to the previously mentioned optical resolution formula, besides increasing the numerical aperture (NA), another approach is to change the wavelength. Using a shorter wavelength light source can significantly improve resolution. This is why the current 193-nanometer DUV (deep ultraviolet) light source needs to be improved to EUV (extreme ultraviolet) lithography. EUV, with a wavelength of only 13.5 nanometers, can provide stronger energy and draw finer lines. The problem is that EUV light cannot use traditional glass lenses. Because of its short wavelength, no effective material has been found to serve as a lens for extreme ultraviolet light. In other words, all traditional glass lenses used in existing machines are unusable; the lenses must be replaced with reflectors. This lens combination is called a total internal reflection optical system. The design must ensure that the light beams avoid each other, and the angle of reflection from the mirror surface must be extremely precise compared to the penetration of the lens. Any unevenness or skew on the mirror surface, even a slight error, can lead to drastic errors, further increasing the design difficulty. Currently, only ASML in the Netherlands can produce EUV exposure machines of this level. Therefore, when ASML was able to produce advanced EUV equipment, various wafer fabs rushed to place orders. However, SMIC, which did not keep up with this wave of EUV exposure machine purchases, stated that it produced 7-nanometer chips in 2021 using a DUV exposure machine and a multi-exposure process. So, it seems that chip manufacturing does not necessarily require an EUV exposure machine? Previously, we discussed many factors affecting pixel pitch. Double and multiple exposures aim to overcome the challenge of repeating the exposure process more than once while keeping linewidth and pixel pitch constant. For example, when the original process limit is 120 nanometers ( meaning the closest distance between two identical components is 120 nanometers), triple exposure can create a 40-nanometer structure. However, the process becomes more complex, requiring the entire circuit diagram to be broken down into three photomasks, and then the pattern for each layer must be assigned. This is similar to slideshows; stacking the three masks results in a complete circuit diagram, no longer limited by pixel pitch limits. In 2021, SMIC completed a 7-nanometer chip manufacturing process using a DUV exposure machine and multiple exposure technology, causing a stir in the industry. However, SMIC's use of older technology to complete the 7nm process is n't exactly new. TSMC also used 193nm immersion DUV multiple exposure to complete the 7nm process in its early days, maintaining a certain yield and stable mass production. What's noteworthy is that SMIC skipped the 10nm node from 14nm and jumped directly to 7nm technology in just two years. This rapid technological leap is comparable to that of major companies like TSMC, Samsung, and Intel. There are various speculations about how SMIC mastered this advanced technology. It could be due to a technology export loophole in the US, or a technology leak from TSMC. What do you think? However, in pursuit of chip quality, every foundry hopes to complete the exposure and etching process in a single exposure. Multiple exposures increase the number of processes. This increases the probability of wafer errors, making it harder to control chip yield. More processes also lengthen chip manufacturing lead times, indirectly increasing overall costs. Naturally, this won't attract customers. After all, TSMC and Samsung have already matured and can use single-exposure EUV technology to manufacture 7nm chips. Customers will naturally flock to higher-quality foundries for foundry services. In September of this year (2022), Zyvex announced its latest lithography system, ZyvexLitho1, which produced 0.7nm chips. Chips manufactured by this lithography machine are mainly used in quantum computers. Although the technology is significantly ahead of ASML's EUV, its production volume is very low and cannot meet market demand. Therefore, it cannot shake the position of EUV for the time being. Today, we will introduce EUV... While crucial to the manufacturing process, it's only one link in the chain. Creating an advanced chip requires the input of key technologies controlled by various countries. This includes US EDA (Engineering Development Association) involvement in chip design and manufacturing, Dutch EUV exposure machines, advanced process technologies from Taiwan and South Korea, and photoresists from Japan or the US. This situation, where each country controls key technologies, creates a balance of mutual need and checks and balances. Recently (2022), the US Department of Commerce directly sent letters to several semiconductor companies, announcing an expanded ban in October on the export of semiconductor manufacturing equipment below 14 nanometers to China. These companies include KLA Corp, Lam Research Corp, and Applied Materials Inc. Reuters points out that direct government notifications can target specific companies, circumventing the long and arduous process of regulatory formulation. The ban was swiftly implemented, but why target these companies? What important roles do they play in the semiconductor industry? Do you understand manufacturing processes? To understand how these bans will affect the semiconductor industry, we must first understand semiconductor manufacturing processes. At the very upstream of semiconductor manufacturing processes are chip design and silicon intellectual property (IIP), responsible for designing integrated circuits. In this episode, we'll discuss the relevant steps in semiconductor manufacturing processes, including deposition, exposure, etching, etc. As for packaging and chip testing, we'll discuss that in the next episode. In the news, we often see round silicon wafers, which are actually smelted from sandy silicon dioxide (SiO2). How is this done? First, graphite is added to silicon dioxide to form crude silicon, and then it is chlorinated with hydrochloric acid. After distillation and purification, high-purity polycrystalline silicon is produced. The " N" here stands for "Nine." Silicon wafers used in solar panels typically require a purity between 5 and 6N, while advanced integrated circuits require polycrystalline silicon with a purity as high as 11N. Then, using the Diesel crystal pulling method, a silicon seed crystal is slowly pulled from the molten polycrystalline silicon solution to form a cylindrical single-crystal silicon ingot. Next, the single-crystal silicon ingot is sliced ​​into wafers, and the edges are ground and polished to obtain the most basic material for semiconductor manufacturing: silicon wafers. Although Taiwan also produces its own wafers, Japanese wafers generally have higher purity. The ability to achieve the previously mentioned 11N is why Japanese companies like Shin-Etsu Chemical and SUMCO account for 60% of the global supply. With the raw silicon wafer, the entire manufacturing process can begin. Simply put, it's a cycle of deposition, exposure, and etching. First, a silicon dioxide or silicon nitride insulating layer is created on the wafer. Then, deposition can proceed. Although the word "wafer" is used, it's actually a three-dimensional structure, like building a house, layer by layer, to create the desired structure. Deposition involves building and cultivating a thin film on the wafer surface, covering it with the desired structure, such as an insulator, semiconductor, or aluminum-copper layer. Next comes the lithography process. In simple terms, the process involves "drawing" the designed semiconductor integrated circuit onto a wafer. This requires first applying a photosensitive material called photoresist onto the wafer. Based on the exposure and development process, photoresists are categorized as positive or negative. Positive photoresists, after exposure, dissolve in the light-exposed areas during development, leaving the unexposed areas as the pattern. For IC products requiring high pattern precision, positive photoresists are typically used to transfer the circuit design pattern. Negative photoresists, on the other hand, dissolve in the unexposed areas during development, leaving the exposed areas as the pattern. Negative photoresists were the first photoresists used in photolithography, offering advantages such as low processing costs. High throughput and other advantages are the core of lithography. As we discussed in our previous video on EUV, it utilizes the optical imaging principle of an exposure machine to focus the photomask pattern onto a photoresist-coated wafer at a 4:1 magnification. However, each transistor layer may have different circuit patterns, some coarse and some fine. This means that each layer of exposure requires a different photomask design to obtain a three-dimensional integrated circuit. Next comes the etching process, where unwanted portions of the deposited thin layer are removed. Etching can be divided into two main types: wet etching using liquid solutions and dry etching using chemical gases, plasmas, or ions. Wet etching using chemical solutions is less expensive and faster. However, the etching direction is isotropic, meaning the etching speed is the same in all directions, resulting in lower accuracy and difficulty in processing intricate patterns. Dry etching using gas, on the other hand, uses plasma ions formed by ions and electrons to complete the etching. Because it can process horizontally and vertically at different speeds, it is more accurate than wet etching, but it takes much longer. Is there a way to have the best of both worlds? Yes, there is: using plasma for both physical and chemical etching. This approach combines the anisotropic advantages of physical etching, which improves the accuracy of the etching position, with the high selectivity of chemical etching, allowing for significantly different etching rates for different materials. This method avoids over-etching, preventing the etching from penetrating to the next layer. Through this repeated deposition or etching cycle, we can stack the desired structure layer by layer. It's important to understand that building any tiny component on a chip requires repeatedly depositing many thin films, etching away unwanted parts again and again to create different blocks of an integrated circuit and the materials that keep each component separate. Advanced logic chip designs typically involve up to 50 or more layers of repeated stacking, while non- logic chips, such as NAND Flash memory, can have stacking designs with over 200 layers. Returning to the initial question, why is this ban targeting these companies? We can see from the process steps we just discussed that Colin Research has mastered many key technologies for semiconductor equipment, especially in etching and thin film deposition processes. Applied Materials' main products are atomic layer deposition, physical and chemical vapor deposition, and related testing. Both of these companies have mastered very important links in the process. KLA-Tec mainly provides semiconductor manufacturing-related process control and yield management services. This is why these three companies are listed as export control companies by the U.S. Department of Commerce, and are prohibited from selling equipment related to advanced processes below 14 nanometers. The controlled countries include China, Russia, North Korea, and Iran. A closer look at this series of major actions by the United States, from lobbying ASML in the Netherlands... The US is not providing EUV exposure machines. With the chip bill finalized in June, it prohibited the export of EDA (Engineering, Technology, and Manufacturing) equipment below 3 nanometers. Now, the ban has been expanded to include companies involved in processes below 14 nanometers. Any company selling products or equipment will need government approval. More companies may face restrictions in the future. The goal is to slow down China's progress in advanced processes below 14 nanometers. The US is gradually imposing a blockade on China across the entire semiconductor technology export chain, from upstream to downstream. The reasons and purposes are interpreted in various ways, but regardless, China will inevitably have to accelerate its semiconductor self-sufficiency rate. Do you think this is possible, based on your understanding of the semiconductor industry? What are the key factors for success or failure? Is this Einglongte? I never thought I'd live to see Vision Pro announced at Apple's WWDC this year. Besides causing a huge stir in the market, Apple's newly launched Mac Pro and Mac Studio are also very eye-catching. Their common feature is that I can't afford them. Their common feature is that they all contain M-series chips, from M2, M2 Max to M2 Ultra. In addition to their powerful performance, their lightweight design allows these devices to remain lightweight; the Vision Pro's weight can also be maintained at 500 grams, without affecting the wearing experience. To achieve computer-like performance in such a small chip, besides the DUV and EUV micro-magnification we've introduced, which progresses from 7nm, 5nm, to 3nm, "advanced packaging" technology plays a more important role in the M-series system-on-a-chip. But what exactly is packaging, and how does it help the M2 achieve high performance and small size? The performance of the M2 chip has already been recognized by consumers. A tiny chip simultaneously contains an 8-core CPU, a 10-core GPU, a 16-core neural network chip, and memory. Small in size but complete in function, this can be seen as another step forward in Moore's Law. On March 24th of this year, Intel co-founder Gordon Moore passed away at his home in Hawaii at the age of 94. His Moore's Law, which has guided the semiconductor industry for nearly 60 years, is gradually approaching its limits. Moore's Law predicts that the number of transistors on an integrated circuit will double approximately every 18 months in the same area, and chip performance will continue to improve. As chip sizes become smaller and smaller, seemingly unable to get any smaller, the voices saying "Moore's Law is dead" are growing louder. However, the fact is that industry leaders such as TSMC, Intel, and Samsung... They still believe Moore's Law will continue and continue to actively invest significant amounts of money, manpower, and resources, hoping to win this nanoscale chip war. Methods to win this war include developing various transistors, such as finned field-effect transistors, wound-loop gate transistors, and bridged-channel field-effect transistors, or investing heavily in Esmore's extreme ultraviolet lithography machine to achieve breakthroughs in miniaturization. You can review our previous video on this topic. In addition, some are focusing on materials science, developing emerging semiconductor materials such as transition metal dichalcogenides or carbon nanotubes. These methods of continuously challenging the limits of physics are known as Deep Moore's Law. However, this path is not a smooth highway, but rather fraught with thorns, or rather, a jumble of Lego bricks. The complexity and investment required for advanced process development increase exponentially, and the return on investment is often disproportionate. We all know not to put all your eggs in one basket. Similarly, semiconductor giants have begun searching for new solutions, pondering how to—no, how— improve the overall performance of chips without shrinking transistors. The answer isn't difficult: since more transistors can't fit in a two-dimensional space, stack them up. This effectively increases the number of transistors in the same area. It's like in a city, where dense populations and limited land lead to towering apartment buildings, each building taller than the last. This method, which doesn't use miniaturized transistors but rather stacks semiconductor circuits layer by layer through system integration to improve chip performance, is considered " More than Moore's Law." The key to this technology lies in packaging. After a silicon wafer undergoes multiple processing steps, we get a wafer with thousands of integrated circuits covering its surface. Don't underestimate it; the value of just one wafer can be as high as $20,000. However, such a large wafer obviously can't fit into your phone; it must undergo packaging before transforming into the semiconductor chip we know. Simply put, packaging is a technology whose task is to remove the integrated circuits from the wafer and place them on a carrier board, allowing the integrated circuits to connect with other circuits and exchange signals. The entire packaging process can be roughly divided into four steps: dicing, die bonding, wire bonding, and encapsulation. First, the silicon wafer is ground thinner and cut into small pieces. At this stage, the integrated circuit is called a bare die. Next, the bare die is bonded to a carrier board, and wire bonding connects the bare die and the metal contacts of the carrier board. The integrated circuit can then transmit or receive signals from the outside world. Finally, epoxy resin is used to mold the chip, completing the familiar chip we know. This step mainly protects the bare die and wire bonding, while also isolating moisture and helping to dissipate heat. As chips continuously pursue high efficiency and low cost, and need to meet different requirements, it is even desirable to include multiple integrated circuits with different functions in a single chip system. These integrated circuits have different specifications and sizes, and may even be produced in different factories. Using nodes from different manufacturing processes or different semiconductor substrates, such as Apple's M2 chip, which simultaneously includes a CPU, GPU, and memory, creates a chip system architecture containing multiple chips called a chiplet. To create a chiplet, traditional packaging involves integrating several pre-packaged chips into a more complete module called a System-in-Package (SIP). Another method is to interconnect several bare dies through a single carrier board to complete the packaging; this approach is called a System-on-a-Chip (SoC). However, both of these methods require a larger footprint and suffer from data transmission delays due to excessively long metal interconnects between chips and dies, failing to meet the needs of high-end chip customers like NVIDIA, AMD, and Apple. To solve these problems, advanced packaging emerged. 3D advanced packaging increases space utilization and improves data transmission bottlenecks by stacking bare dies. The difference in transmission speed between it and traditional packaging is like driving from Taipei to Yilan. Traditional packaging requires navigating the winding Provincial Highway 9, while advanced packaging cuts the curves and creates a tunnel connecting the two cities, making data exchange more convenient and faster. The biggest advantage of advanced packaging is that it significantly shortens the distance between metal interconnects between different bare dies, thus greatly improving transmission speed and reducing power loss during transmission. For example, in a traditional 2D SoC, if circuit A needs to transmit data to circuit C, it must cross the entire diagonal distance of the system. However, using 3D stacking, the C chip can be stacked... Placed directly above chip A, the silicon through-via (TSV) technology penetrates the thinned silicon substrate, connecting the two circuits with ultra-high-density vertical interconnects. The distance between them is reduced dramatically. Furthermore, 3D stacking reduces area consumption, with minimal increase in volume. Therefore, we can expect that future smartphones, tablets, and headsets like the Vision Pro will not only have more features but also be more compact. It's worth mentioning that advanced packaging can also reduce production costs. Because 3D stacking increases the equivalent transistor count per unit area, chip design can utilize more mature and lower-cost process technology nodes, achieving performance comparable to single-layer advanced technology nodes. While advanced packaging offers many advantages, as a new technology, it still faces numerous challenges and problems. Firstly, advanced packaging places high demands on die flatness and chip alignment. If, during stacking, a contact fails to connect properly, it will result in lower yield. Secondly, integrated circuits generate energy losses during operation, causing temperature increases. Advanced packaging brings the dies closer together, leading to cross- conduction and making heat dissipation even more difficult. This can reduce chip performance or, in severe cases, cause product failure. While heat dissipation is not yet fully resolved in advanced packaging, it can be optimized through thermal simulation, using materials with high thermal conductivity, or designing thermally conductive structures. Establishing a yield testing process is also crucial. Imagine if, before stacking, individual bare dies weren't tested for compliance, and a qualified A-chip was mistakenly combined with a defective B-chip. Not only would the resulting 3D IC be merely decorative, but the manpower, resources, and money invested in the preceding processes would also be wasted. The trade-off between yield and cost is a complex issue that needs to be explored. To ensure optimal yield, the best approach is to test every step. However, this would correspondingly increase production costs and manufacturing time. Therefore, how to test, when to test, and how many tests to perform is a rather profound subject. We are still learning about this and welcome expert guidance in the comments. What we've learned here is that packaging is not just about stacking Lego bricks; there's much more to it than meets the eye. The ability to achieve both small size and high speed is precisely what makes the M2 chip in the Vision Pro so powerful. Currently, Apple has entrusted all M-series chips to TSMC in Taiwan, along with the 3DFabric Alliance led by TSMC, for production. Besides lithography, what other cutting-edge technologies does TSMC possess? Advanced packaging has become a fiercely contested area for major semiconductor manufacturers, and TSMC is no exception. In 2022, TSMC integrated its advanced packaging technologies to establish the open innovation platform 3DFabric Alliance. This alliance includes nineteen domestic and international companies, such as ASE, E- Hwa Computer, Micron, and even Samsung Amkor from South Korea. This platform can provide three advanced packaging technologies based on different product needs and cost considerations. First, CoWoS... InFO and its two technologies utilize the concept of 3D stacking, stacking bare dies through silicon interposers or insulating thin films to shorten interconnects and make chips thinner and smaller. For example, at this year's WWDC, in addition to Vision Pro, Apple also launched the M2 Ultra chip, which can be assembled with two M2 Max chips. The custom packaging technology it uses, Ultra Fusion, is presumably based on the architecture developed from InFO. Another highly anticipated technology is the "true" 3D stacking technology called SoIC, which can directly bond two bare dies or wafers face to face. It is the industry's first realization of high-density multi-die vertical stacking. It has already entered small-scale mass production by the end of 2022 and is suitable for process nodes below 10 nanometers. Even more impressively, these three technologies can be integrated with each other. Simultaneously using advanced packaging technologies like Transformers to optimize chip efficiency, we can expect more powerful chips and new applications in the future. As chiplet technology, which leverages advanced packaging techniques, matures, we will see more and more amazing products like Vision Pro. How can chips be made so tiny, down to each thin film layer? To create more powerful chips, major manufacturers in the semiconductor industry chain are constantly pulling out all the stops, developing new designs like loop gates and 3D packaging, and introducing extreme ultraviolet lithography to etch even smaller circuits. But don't forget, to create these complex designs, you first need a good substrate, that is, you need a substrate that can be mounted on the wafer. Growing layers of material only atom thick has become a key aspect of semiconductor manufacturing, a process known as "thin film fabrication." The challenge lies in precisely creating the thinnest possible layers, only atom thick, while maintaining perfect uniformity. For example, 3 nanometers must be exactly 3 nanometers— no more, no less. The only method for this is ALD ( Atomic Layer Deposition) technology. Thanks to ASM, a semiconductor equipment manufacturer with over 50 years of experience and years of expertise in this field, for sponsoring this episode. Let's explore how these tiny semiconductor chips are made and what ALD actually is. Do you know how these tiny transistors are made? The semiconductor industry is now enormous, with renowned companies like TSMC being its pillars. However, it still cannot break free from the entire industrial chain and independently complete chip manufacturing. This is because a large number of materials and equipment used in the chip manufacturing process, such as wafers, photoresists, and exposure machines, need to be supplied by companies scattered around the world. This massive industrial chain fully reflects how complex and difficult it is to make a chip. Even Senku Ishigami said that making semiconductors is hellishly difficult. But in essence, from a production technology perspective, the key to chip manufacturing lies in "lithography." What does lithography do? We introduced it in detail in this episode before. Here, we will quickly review it. Simply put, lithography is about "covering" materials layer by layer and then performing deposition, exposure, and etching. The three-step process, like building a house, gradually builds up the entire chip. Specifically, engineers first create a silicon dioxide or silicon nitride insulating layer on the wafer. Next, they perform the first deposition, placing the desired material, which could be an insulator, semiconductor, or copper conductive layer. Then, to etch the desired pattern onto this material, a photoresist is applied. Through exposure, the photoresist is cleaned, leaving only the desired pattern. The EUV ( Extreme Ultraviolet) lithography machine, which we often hear about, is used here. Its power lies in its ability to etch finer and more complex patterns to handle various new designs. Finally, the exposed wafer is "etched." Materials not protected by photoresist are removed, leaving a pattern identical to the photoresist. After one cycle, a different material is used, and the deposition, exposure, and etching process is repeated, much like building a house, layer by layer, ultimately creating a multifunctional skyscraper. Indeed, you can probably see that to create a thin and stable chip, the first step is a poor substrate. This is like the quality of clay used in hand-thrown pottery; if the clay itself is flawed, no matter how skillful your hands are, you can't create a good piece. But actually, growing layers of material on a wafer is not simple. In thin-film fabrication, materials scientists have developed many options to handle this task. We can broadly divide them into two categories: physical and chemical. Physical thin-film processes include evaporation and sputtering. Ion deposition, physical vapor deposition, pulsed laser deposition, and molecular beam epitaxy are some of the methods used in thin film fabrication. Chemical thin film fabrication includes chemical vapor deposition (CVD) and chemical liquid phase deposition (CLD). Different materials and temperature conditions require different thin film fabrication processes. In semiconductor manufacturing, CVD is a very common method. The atomic arrangement of a compound significantly affects the physical properties of the material, and even slight changes in temperature, pressure, or reactant concentration can completely alter the final product. Therefore, semiconductor materials such as silicon dioxide, silicon carbide, and silicon nitride are particularly suitable for CVD. CVD grows the desired material on the substrate through chemical reactions. The CVD process itself is not difficult; it uses hydrogen and argon gas... These "carrier gases," used to carry raw materials, bring the gases or raw material vapors to be reacted into the reaction chamber. When two or more raw materials are mixed here, a chemical reaction occurs on the heated target substrate, gradually growing our target material. This is similar to AB glue; the two glues themselves have no adhesion, but when mixed together, they become sticky. Sounds simple, right? But it's actually quite complex. From the selection of carrier gases, their temperature, and the concentration of reactants, to the substrate temperature, reaction time, and even the substrate's position in the reaction chamber from the gas inlet, all these factors affect the thickness and uniformity of the deposit. For any company and equipment manufacturer, these parameters are truly the most valuable. Moreover, besides simply growing thin films, the CVD-derived "epitaxy" technology is also very important. For example, if you want to grow another layer of silicon on a silicon wafer, you would naturally want the two silicon layers to be aligned and aligned, rather than misaligned or having inconsistent lattice sizes. Needless to say, the aesthetics of epitaxy are a key technological challenge for each company. However, while CVD is our most common thin-film fabrication method, as we pursue Moore's Law and develop 3D, complex transistor structures, thin films also need to conform to the structure and pursue higher precision and more consistent quality. This doesn't mean CVD is unusable. In fact, both CVD and other thin-film fabrication technologies still hold important positions in semiconductor manufacturing. The key point is that as competition for smaller semiconductor nodes intensifies, chip design becomes increasingly complex. For example, this is the structure of a traditional planar transistor. This is the current mainstream FinFET fin field-effect transistor structure. This one, on the other hand, is the GAA (Gateway Alloy) gate transistor that everyone is currently working hard to develop. Can you see the difference? That's right, it's a major test for thin-film technology. For example, if you use such a complex structure for CVD, some areas will be like cleaning the bottom of a cup—there will always be some spots where the dish soap doesn't stick. If you suddenly increase the amount of dish soap, it won't affect the cup, but for the semiconductor, the areas closest to the surface will grow a significantly thicker layer than other areas. How do we solve this problem? Materials scientists' idea is to find a way to stop the growth of this thin film when it reaches a certain height. This way, if we increase the reaction time... This ensures that a thin film grows everywhere, but growth stops once a specified height is reached in each area, thus guaranteeing uniform film thickness. This method is called Atomic Layer Deposition (ALD). As the name suggests, deposition occurs on an atomic layer basis. How is this achieved? ALD is essentially a modified version of Chemical Vapor Deposition (CVD). The gaseous precursor used exhibits a significant "self-limiting phenomenon," allowing us to control the deposition of only one atomic layer at a time. Furthermore, the reaction is split into two steps. In the first stage of ALD, the first precursor is injected and reacts with the substrate surface. In this stage, it's crucial to ensure that the precursor only reacts with the substrate and does not continuously accumulate. This results in a thin film... There is absolutely only one layer of molecules. This reaction gradually stops as the surface space becomes saturated; this is called the self-limiting phenomenon. At this point, a second precursor is injected, reacting with the first precursor already attached to the substrate to synthesize the material we want, completing the thin film process. Specifically, the design of the first and second precursors becomes crucial. Taking zinc oxide coating as an example, the first precursor is diethylzinc. After zinc reacts with the substrate, other diethylzinc molecules that try to approach are blocked by the ethyl group behind it, ensuring that only one layer of diethylzinc is ultimately on the substrate. Then, gases such as argon are used to flush away the reacting precursors before introducing the second precursor. Water reacts chemically with diethylzinc. The final zinc oxide is formed. The byproduct ethane is then washed away again with other gases. At this point, only zinc oxide, firmly bonded to the substrate, remains on the substrate. One cycle of ALD is complete, but it's not over yet. If you want to grow more complex structures, such as zinc alumina (AZO), you can continue the cycle, adding more layers of zinc oxide and aluminum oxide on top of the original structure. After repeating this process several times, a transparent conductive film only a few atoms thick is created. Finally, the final form of ALD can withstand almost all process conditions. Do you know who the leading manufacturer in the ALD field is? ASM is a world-leading semiconductor equipment manufacturer with a history of over 50 years, since Arthur del Prado in 1968. Since its founding in the Netherlands, ASM has been committed to advancing advanced semiconductor manufacturing technologies. In 2007, ASM launched the Pulsar ALD, becoming the first deposition equipment used for mass production of high-kJ metal gate logic devices. To date, ASM not only holds over 55% market share in the ALD market but also plays a significant role in fields such as PECVD epitaxy. Of course, ALD is clearly not the end of thin-film manufacturing. As a leading semiconductor equipment manufacturer, ASM must continue to develop new technologies to maintain its leading advantage. For example, the PE in PEALD stands for Plasma Enhanced, so this improved technology is called plasma atomic layer deposition. The approach is the first step in ALD, using plasma... Hydrogen, oxygen, and nitrogen gases are ionized into ions. These gas ions, such as oxygen free radicals, pre-oxidize the precursor and simultaneously oxidize the surface atoms of the substrate, creating unstable "dangling bonds" lacking electron pairings. The activated substrate and precursor are like a couple waiting for each other to confess their feelings; with the help of plasma as matchmaker, they fall in love and are brought together. This solves the problem of insufficient precursor reactivity that ALD often encountered. Moreover, PEALD not only has a lower reaction temperature but also accelerates the reaction rate, thus meeting more process requirements. In the future, ALD technology will continue to be seen in GAA (Gateway Arc-on-Aperture) transistors and other processes. That concludes our introduction to thin-film manufacturing processes for now. However, if you have any questions about thin-film processes or other semiconductor manufacturing technologies, please leave a comment and we'll discuss them in more detail. Hello everyone, the device I have here is Google's new Pixel 7 Pro. Starting with the previous generation Pixel 6, the core of this device has been changed to Google's self-developed Tensor chip. However, judging from the Geekbench benchmark results for the Pixel 7 Pro, it seems disappointing. The Tensor G2 chip not only lags behind the Qualcomm Snapdragon 8 Gen 1 chip currently used in Android flagship models, but it's even inferior to last year's Snapdragon 888. Why? Surprisingly, Google expressed "satisfaction" with this relatively low score. What's going on? Is it because we can't bear to criticize our own creation, or do Tensor chips truly possess exceptional capabilities? Monika Gupta, Google's product director for chips, stated that their chip design focuses on machine learning needs five years from now. Traditional benchmark scores were meaningful at times, but AI innovation has changed the era, and traditional benchmark tests are no longer that important. Although people rarely use their phones for more than five years now, we have indeed seen a complete leap in AI development this year. Google's Tensor chip is touted as a chip specifically designed and built for AI. Let's open the processor, Google Tensor, and take a look. Inside, we find the CPU and GPU we are familiar with. The small section in the upper left corner is the TPU (Tensor Processing Unit), which has AI computing capabilities. To understand the TPU... Let's first look at how its predecessors, the CPU and GPU, work. Whether it's a mobile phone, a computer, or a supercomputer, the common architecture of modern computers uses the von Neumann architecture, designed based on the Turing machine concept. This is a conceptual architecture that combines program instruction memory and data memory. This programmable computer architecture has been used ever since it was proposed in 1945. In this architecture, besides input/output devices, there are three main structures: memory, the control unit (CU), and the arithmetic logic unit (ALU). In your computer's mainframe, the CU and ALU are both contained within the CPU, also known as the Central Processing Unit. Memory, on the other hand, is distributed throughout the computer in different forms and is divided into registers according to access speed. Register, Cache, Main Memory, and Mass Storage (MSS) correspond to SRAM, DRAM, and hard drives in our hardware. The lower the level, the slower the access speed, but the lower the storage cost. The Arithmetic Logic Unit (ALU) is responsible for calculations, performing basic operations such as addition, subtraction, multiplication, division, logical judgment, and shifting through logic gates. Through repeated calculations, it completes complex programs. Integrating different logic gates into a single chip is no easy task. You can watch our previous video on semiconductor manufacturing processes to see how the semiconductor industry makes chips. Besides the sophisticated ALU, another crucial task is process management, which is the main job of the control unit. This is to accelerate calculations. The control unit (CU) analyzes tasks, placing the necessary data and programs into the closest and fastest access register to the arithmetic logic unit (ALU). While waiting for the ALU to complete its task, the CU doesn't remain idle; it determines the next workflow, pre-loading data needed later into the cache and main memory. After the ALU finishes, it assigns the next task to the CPU, placing the semi-finished product into the next register, awaiting further computation. Simply put, the CPU is like a factory; the ALU is the processing machine; the hard drive is the large warehouse; registers and caches are the boxes storing raw materials and semi-finished products on the production line; and the control unit acts as the conveyor belt on the assembly line. And robotic arms continuously transport raw materials and semi-finished products to the next station, while controlling the logistics between the factory and warehouse to maximize efficiency. With the development of technology, the amount of tasks that people need computers to process is becoming increasingly enormous. Do you know how much information a photo you casually take contains? A 1080P photo contains 1920×1080 pixels, a total of 2,073,600 pixels. And that's not all. In a color photo, each pixel also contains three values: RGB. If it's a PNG image with transparency, there's an additional alpha value. That means a single photo has 8 million elements to process. Not to mention that many mobile phones can now shoot at 4K or higher resolutions. This is extremely demanding on the CPU, because the CPU only has one production line. What we can do is increase the number of production lines. Information engineers also discovered that the bottleneck in image processing isn't the difficulty of the calculations, but rather the sheer volume of work. Therefore, instead of increasing the processing speed of the arithmetic logic unit, we should renovate the existing factory, placing as many identical production lines as possible within the factory. Large storage spaces like warehouses can be shared by all production lines. This not only increases the processing power per unit volume but also allows for the production of more items in the same amount of time, reducing the processing time for a single image. In 1999, NVIDIA, a major graphics card manufacturer, first proposed the idea of ​​separating the graphics processor and published the first GPU (Graphics Processing Unit) designed to accelerate graphics processing. The GeForce 256 was the first graphics card in history. A single GPU contains hundreds to thousands of ALUs (Arithmetic Logic Units). It's like cramming many small CPUs onto the same graphics card. During image processing, the control unit assigns each pixel to different ALUs. When everyone is performing the same task— for example, simultaneously increasing red or decreasing opacity—the GPU can significantly improve processing efficiency. This is why most cryptocurrency miners use GPUs as their mining tools. The actual calculations miners perform aren't difficult; the key is repeatedly calculating and handling the massive workload of the " proof-of-work" problem. GPU acceleration is the optimal solution. However, with the development of social media, the demand for image processing technology has increased. And it also becomes more difficult. Yes, I'm talking about the filters you often use. Face recognition and background removal functions are much more complex than simply adjusting the brightness and contrast of a photo. A computer needs to be able to identify objects, which falls under the category of artificial intelligence. But don't worry, artificial intelligence isn't as complicated as you think. For a computer, it's just adding a tiny bit more work. Take a photo of me, for example. To identify that this is "Zheng Gui," we need one processing step to compare whether there are eyes with the same shape as mine in the photo. Another step analyzes whether there is a mouth like mine. Yet another step checks whether there are ears like mine, and so on. We use these comprehensive consultations for face recognition. To improve accuracy... This involves continuously adding parameters, such as the presence or absence of glasses, wrinkles on the face, hairstyle, etc. In addition, it's necessary to consider the subject's rotation within the photo, the contrast of light and shadow, and the possibility of the subject changing clothes or removing glasses. In each calculation, the AI ​​uses this filter to search the photo from left to right and top to bottom for features matching these parameters. Each comparison assigns a score; a higher total score indicates a higher probability of matching the filter's target. It's somewhat like playing Minesweeper. When a high score appears, congratulations, you've found the target! This method is called a convolutional neural network, a type of neural network widely used in image recognition. Besides improving the accuracy of image recognition, it also modifies... The number of filters, the speed of filter movement, and the parameters of shared filters can all reduce the number of matrix operations and speed up neural network calculations. However, even so, the workload is still much more complex than traditional image processing. To cope with the massive matrix operations, our protagonist, the TPU tensor processing unit, was born. Since the key to convolutional neural networks is matrix operations, let 's create a chip with particularly fast matrix operations. We know that matrix multiplication involves multiplying the elements of two matrices together; in essence, it's just a more complex form of addition, subtraction, multiplication, and division. The TPU uses a systolic array for handling matrix operations, which is much faster than the separate ALUs in a GPU. The data moves between the various ALUs, each specializing in a specific part, with everyone working together to complete the task. If the GPU is like adding more assembly lines in a factory, then the TPU is like further subdividing those lines. Those who assemble the wheels only assemble the wheels, and those who paint only paint. This has two advantages: first, each person's workload is reduced, meaning the size of each ALU can be further reduced; second, the process of transferring semi-finished products can occur directly between ALUs, eliminating the need to temporarily store and retrieve them, significantly reducing storage and retrieval time. With this architecture, compared to a GPU that can only hold approximately 4000 cores, the TPU can hold... With a total of 16,000 cores (128x128), and because each core has a smaller workload, the computing speed is faster and the power consumption is lower. Actually, TPUs are nothing new. In 2016, AlphaGo, which defeated South Korean professional Go player Lee Sedol, relied on 48 TPUs and convolutional neural network technology to achieve its goal. How did it do it? For AlphaGo, playing Go is essentially performing a complex image recognition task. The Go board is like a 19-pixel image, but besides being able to immediately identify black and white stones, each pixel contains other parameters, such as the number of "liberties" of a stone, whether the stone is being captured, etc. AlphaGo consulted Go experts... For each point, 48 parameters were defined, so the amount of data on the entire chessboard changed from a 19x19 matrix to a 19x19x48 matrix. This massive data matrix is ​​called a tensor, which is the "T" in TPU representing a tensor. The analysis of the entire chessboard situation and the determination of the next move are done through 5x5 filters. AlphaGo used a total of 192 filters to determine the current situation and the next move. After the neural network was completed, 48 TPUs were used to handle this massive computational load. Finally, to the amazement of audiences worldwide, it successfully defeated Lee Sedol, writing a historic page in AI history. Of course, this was Google's AI. The dream didn't stop there. Following AlphaGo, Google continued to develop AlphaStar, designed for StarCraft battles; AlphaFold, specializing in predicting protein structures; and AlphaTensor, optimized for tensor computation. Many of the Google services we frequently use also utilize TPUs for optimization. For example, Google, the world's largest search engine, and Google Maps translation heavily rely on TPUs and neural networks for acceleration. In 2021, Google further integrated TPUs into its mobile phone products, namely the Google Tensor we mentioned earlier. This year, the Pixel 7 features the upgraded Google Tensor G2. Google states that the new AI chip can accelerate machine learning by 60%, speed up voice assistant processing, and add functionality, such as removing background noise during calls and improving call quality. However, the most impressive aspect is image processing. AI has enabled blur restoration, not only correcting hand shakiness but also making old photos clearer. With the help of AI, mobile phones and computers can do more and more. Besides Google's TPU, other companies are also moving towards AI chips, including Apple, Qualcomm, MediaTek, and Cambricon from China, all of which have released their own neural network processors. The convolutional neural network introduced today is only one type of neural network, a small part of machine learning. Beyond image recognition, many more technologies are needed to assist in other areas. In recent years, AI has already transcended imagination; anyone can experience it firsthand through mobile phones and computers. The number of future applications in creative and technological fields will only increase. That said… To differentiate themselves, new smartphones are increasingly emphasizing the differences in their own chip designs and performance. For you, what chip features are most important? Is it the ability to accelerate deep learning and improve photo and video quality with AI? Or is it power saving and long battery life? Or do you think the manufacturing process is key, as long as you choose TSMC? Or do you think as long as it doesn't overheat, everything else is fine? If you have more questions and thoughts about smartphone chips, feel free to leave a comment and let us know. Okay, that's all for this episode. Special thanks to Google for providing the Pixel 7 Pro phone and watch for our experience. Remember to subscribe to the PanSci channel, turn on notifications, and join our channel membership to stay updated on more exciting scientific knowledge. See you next time on scientific topics.